ST STM32L4+ Series Reference Manual page 272

Reset and clock control (RCC)
Bits 14:8 PLLSAI2N[6:0]: PLLSAI2 multiplication factor for VCO
Caution:
Bits 7:4 PLLSAI2M: Division factor for PLLSAI2 input clock
Caution:
Bits 3:0 Reserved, must be kept at reset value.
6.4.7 Clock interrupt enable register (RCC_CIER)
Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
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Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLLSAI2 is disabled.
VCOSAI2 output frequency = VCOSAI2 input frequency x PLLSAI2N
with 8 =< PLLSAI2N =< 127
0000000: PLLSAI2N = 0 wrong configuration
0000001: PLLSAI2N = 1 wrong configuration
...
0000111: PLLSAI2N = 7 wrong configuration
0001000: PLLSAI2N = 8
0001001: PLLSAI2N = 9
...
1111111: PLLSAI2N = 127
The software has to set correctly these bits to ensure that the VCO
output frequency is between 64 and 344 MHz.
Set and reset by software to divide the PLLSAI2 input clock before the VCO.
These bits can be written only when PLLSAI2 is disabled.
VCO input frequency = PLLSAI2 input clock frequency / PLLM with 1 <= PLLSAI2M <= 16
0000: PLLSAI2M = 1
0001: PLLSAI2M = 2
0010: PLLSAI2M = 3
0011: PLLSAI1M = 4
0100: PLLSAI2M = 5
0101: PLLSAI2M = 6
0110: PLLSAI2M = 7
0111: PLLSAI2M = 8
1000: PLLSAI2M = 9
...
1111: PLLSAI2M= 16
The software has to set these bits correctly to ensure that the VCO input
frequency ranges from 2.66 to 8 MHz.
28 27 26 25
Res. Res. Res.
12 11 10 9
HSI48 LSECS
Res.
RDYIE SIE
rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
PLLSAI PLLSAI
Res. 2RDYI 1RDYI
RDYIE
E E
rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res.
5 4 3 2
PLL HSE HSI MSI
RDYIE RDYIE RDYIE
rw rw rw rw
RM0432
17 16
Res. Res.
1 0
LSE LSI
RDYIE RDYIE
rw rw