ST STM32L4+ Series Reference Manual page 294

Reset and clock control (RCC)
6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x60
Reset value: 0x0000 0000
Access: word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29
Res. Res. Res. Res.
15 14 13
USART TIM8E SPI1E
Res.
1EN N
rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 DSIEN: DSI clock enable
Set and cleared by software.
0: DSI clock disabled
1: DSI clock enable
Bit 26 LTDCEN: LCD-TFT clock enable
Set and cleared by software.
0: LTDC clock disabled
1: LTDC clock enable
Bit 25 Reserved, must be kept at reset value.
Bit 24 DFSDM1EN: DFSDM1 timer clock enable
Set and cleared by software.
0: DFSDM1 clock disabled
1: DFSDM1 clock enabled
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2EN: SAI2 clock enable
Set and cleared by software.
0: SAI2 clock disabled
1: SAI2 clock enabled
Bit 21 SAI1EN: SAI1 clock enable
Set and cleared by software.
0: SAI1 clock disabled
1: SAI1 clock enabled
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM17 timer clock enable
Set and cleared by software.
0: TIM17 timer clock disabled
1: TIM17 timer clock enabled
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28 27 26 25
LTDCE
DSIEN Res.
N
rw rw
12 11 10 9
TIM1E
Res. Res.
N N
rw rw
24 23 22
DFSD SAI2E SAI1E
Res.
M1EN N
rw rw
8 7 6
Res. FWEN Res.
rs
RM0432 Rev 6
21 20 19 18
TIM17E
Res. Res.
N N
rw rw
5 4 3 2
Res. Res. Res. Res.
RM0432
17 16
TIM16E TIM15E
N N
rw rw
1 0
SYSCF
Res.
GEN
rw