ST STM32L4+ Series Reference Manual page 425

RM0432
18/24-bit mode (RGB888)
This mode needs data reordering.
1. The Red and the Blue have to be swapped (setting the RBS bit)
2. The MSB and the LSB bytes of an half-word as to be swapped (setting the SB bit)
Transfer
Order
Data Bus D15 D14 D13 D12 D11 D10
Colors R7 R6 R5 R4 R3 R2
1st pixel
Steps
Original data ordering
Data ordering after red and blue
swap (RBS set)
Data ordering after byte swapping
(SB set)
13.3.10 DMA2D AHB master port timer
An 8-bit timer is embedded into the AHB master port to provide an optional limitation of the
bandwidth on the crossbar.
This timer is clocked by the AHB clock and counts a dead time between two consecutive
accesses. This limits the bandwidth usage.
The timer enabling and the dead time value are configured through the AHB master port
timer configuration register (DMA2D_AMPTCR).
Figure 37. Intel 8080 18/24-bit mode (RGB888)
1
16-bit Data
D9 D8 D7 D6 D5 D4 D3 D2
R1 R0 G7 G6 G5 G4 G3 G2 G1 G0
Table 71. Output FIFO byte reordering steps
@ + 3
B [7:0]
1
G [7:0]
2
R [7:0]
3
Setting the RBS bit
R [7:0]
1
G [7:0]
2
B [7:0]
3
Setting the SB bit
B [7:0]
0
R [7:0]
2
G [7:0]
3
RM0432 Rev 6
Chrom-ART Accelerator controller (DMA2D)
D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
B7 B6 B5 B4 B3 B2
16.7M colors
@ + 2
R [7:0]
0
B [7:0]
2
G [7:0]
3
B [7:0]
0
R [7:0]
2
G [7:0]
3
R [7:0]
1
G [7:0]
2
B [7:0]
3
2
16-bit Data
D7 D6 D5 D4 D3 D2
B1 B0 R7 R6 R5 R4 R3 R2 R1 R0
2nd pixel
@ + 1 @ + 0
G [7:0] B
0 0
R [7:0] G
1 1
B [7:0] R
3 2
G [7:0] R
0 0
B [7:0] G
1 1
R [7:0] B
3 2
R [7:0] G
0 0
G [7:0] B
1 1
B [7:0] R
2 3
D1 D0
MSv42079V2
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
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