ST STM32L4+ Series Reference Manual page 460

Chrom-GRC™ (GFXMMU)
14.4 Graphic MMU interrupts
An interrupt can be produced on the following events:
•
Buffer 0 overflow
• Buffer 1 overflow
•
Buffer 2 overflow
• Buffer 3 overflow
•
AHB master error
Separate interrupt enable bits are available for flexibility.
Interrupt event
Buffer 0 overflow
Buffer 1 overflow
Buffer 2 overflow
Buffer 3 overflow
AHB master error
460/2301
Table 74. Graphic MMU interrupt requests
Event flag
B0OF
B1OF
B2OF
B3OF
AMEF
RM0432 Rev 6
RM0432
Enable control bit
B0OIE
B1OIE
B2OIE
B3OIE
AMEIE