ST STM32L4+ Series Reference Manual page 316

Reset and clock control (RCC)
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 OCTOSPI2_DLY: Delay sampling configuration on OCTOSPI2 to be used for internal sampling
clock (called feedback clock) or for DQS data strobe.
Set and reset by software.
Bits 3:0 OCTOSPI1_DLY: Delay sampling configuration on OCTOSPI1 to be used for internal sampling
clock (called feedback clock) or for DQS data strobe.
Set and reset by software.
6.4.34 RCC register map
The following table gives the RCC register map and the reset values.
Off-
Register
set
RCC_CR
0x00
Reset value
0x04 RCC_ICSCR
Reset value
0x08 RCC_CFGR
Reset value
RCC_PLL
PLLPDIV[4:0]
CFGR
0x0C
0 0 0 0 0 0 0 0
Reset value
316/2301
0000: 1 unitary delay
0001: 2 unitary delays
0010: 3 unitary delays
...
1111: 16 unitary delays
0000: 1 unitary delay
0001: 2 unitary delays
0010: 3 unitary delays
...
1111: 16 unitary delays
Table 38. RCC register map and reset values
0 0 0 0 0 0
HSITRIM[6:0]
1 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x
MCOP
MCOSEL
RE
[3:0]
[2:0]
0 0 0 0 0 0 0
PLLR
[1:0]
0 0 0 0
HSICAL[7:0]
0
PLL
Q
[1:0]
0 0 0 0 0
RM0432 Rev 6
MSIRANG
[3:0]
0 0 0 0 0 1 1 0 0 0 1 1
MSITRIM[7:0]
PPRE2 PPRE1
HPRE[3:0]
[2:0] [2:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0
PLLN PLLM
[6:0] [3:0]
0 0 1 0 0 0 0 0 0 0 0
RM0432
E
MSICAL[7:0]
SWS SW
[1:0] [1:0]
PLL
SRC
[1:0]
0 0