ST STM32L4+ Series Reference Manual page 583

RM0432
Bit 22 APMS: Automatic-poll mode stop
This bit determines if the automatic polling is stopped after a match.
0: Automatic-polling mode is stopped only by abort or by disabling the OCTOSPI.
1: Automatic-polling mode stops as soon as there is a match.
This bit can be modified only when BUSY=0
Bit 21 Reserved, must be kept at reset value.
Bit 20 TOIE: Timeout interrupt enable
This bit enables the timeout interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 19 SMIE: Status match interrupt enable
This bit enables the status match interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 18 FTIE: FIFO threshold interrupt enable
This bit enables the FIFO threshold interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 17 TCIE: Transfer complete interrupt enable
This bit enables the transfer complete interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 16 TEIE: Transfer error interrupt enable
This bit enables the transfer error interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 FTHRES[4:0]: FIFO threshold level
This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes
the FIFO threshold flag FTF in OCTOSPI_SR, to be set.
0: FTF is set if there are 1 or more free bytes available to be written to in the FIFO in Indirect-
write mode, or if there are 1 or more valid bytes can be read from the FIFO in Indirect-read
mode.
1: FTF is set if there are 2 or more free bytes available to be written to in the FIFO in Indirect-
write mode, or if there are 2 or more valid bytes can be read from the FIFO in Indirect-read
mode.
...
31: FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-write
mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode.
If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before
changing the FTHRES[4:0] value.
RM0432 Rev 6
Octo-SPI interface (OCTOSPI)
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