ST STM32L4+ Series Reference Manual page 531

RM0432
Table 111. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)
Bit number
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Table 112. FMC_BTRx bitfields (Synchronous multiplexed write mode)
Bit number
31-30
29:28
27-24
23-20
19-16
15-8
7-4
3-0
Bit name
To be set to 1 if the memory supports this feature, to be kept at 0
WAITEN
otherwise.
WREN 0x1
WAITCFG 0x0
Reserved 0x0
WAITPOL to be set according to memory
BURSTEN no effect on synchronous write
Reserved 0x1
FACCEN Set according to memory support
MWID As needed
MTYP 0x1
MUXEN As needed
MBKEN 0x1
Bit name
DATAHLD Don't care
ACCMOD 0x0
DATLAT Data latency
0x0 to get CLK = HCLK
CLKDIV
0x1 to get CLK = 2 × HCLK
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
DATAST Don't care
ADDHLD Don't care
ADDSET Don't care
RM0432 Rev 6
Flexible static memory controller (FSMC)
Value to set
Value to set
531/2301
554