ST STM32L4+ Series Reference Manual page 505

RM0432
FMC signal name I/O
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits (26 address lines).
18.7.2 Supported memories and transactions
Table 92
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.
Device
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
Table 91. 16-Bit multiplexed I/O PSRAM (continued)
O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
O
O
O
I
O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
below shows an example of the supported devices, access modes and
Table 92. NOR Flash/PSRAM: example of supported memories
Mode
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
Flexible static memory controller (FSMC)
Output enable
Write enable
Address valid PSRAM input (memory signal name: NADV)
PSRAM wait input signal to the FMC
and transactions
AHB
Memory
R/W data
data size
size
R 8 16
W 8 16
R 16 16
W 16 16
R 32 16
W 32 16
R - 16
R 8 16
R 16 16
R 32 16
RM0432 Rev 6
Function
Allowed/
not Comments
allowed
Y
N
Y
Y
Y Split into 2 FMC accesses
Y Split into 2 FMC accesses
N Mode is not supported
N
Y
Y
-
-
-
-
-
-
-
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