ST STM32L4+ Series Reference Manual page 258

Reset and clock control (RCC)
6.4 RCC registers
6.4.1 Clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 0063. HSEBYP is not affected by reset.
Access: no wait state, word, half-word and byte access
31 30 29
PLLSAI PLLSAI
Res. Res.
2RDY 2ON
r
15 14 13
Res. Res. Res. Res.
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 PLLSAI2RDY: SAI2 PLL clock ready flag
Set by hardware to indicate that the PLLSAI2 is locked.
0: PLLSAI2 unlocked
1: PLLSAI2 locked
Bit 28 PLLSAI2ON: SAI2 PLL enable
Set and cleared by software to enable PLLSAI2.
Cleared by hardware when entering Stop, Standby or Shutdown mode.
0: PLLSAI2 OFF
1: PLLSAI2 ON
Bit 27 PLLSAI1RDY: SAI1 PLL clock ready flag
Set by hardware to indicate that the PLLSAI1 is locked.
0: PLLSAI1 unlocked
1: PLLSAI1 locked
Bit 26 PLLSAI1ON: SAI1 PLL enable
Set and cleared by software to enable PLLSAI1.
Cleared by hardware when entering Stop, Standby or Shutdown mode.
0: PLLSAI1 OFF
1: PLLSAI1 ON
Bit 25 PLLRDY: Main PLL clock ready flag
Set by hardware to indicate that the main PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: Main PLL enable
Set and cleared by software to enable the main PLL.
Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be
reset if the PLL clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
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28 27 26 25
PLLSAI PLLSAI PLLRD
1RDY 1ON Y
rw r rw r
12 11 10 9
HSIAS HSIRD HSIKER
FS Y ON
rw r rw
24 23 22
PLLON Res. Res. Res.
rw
8 7 6
HSION MSIRANGE[3:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
CSS HSE
Res.
ON BYP
rs rw
5 4 3 2
MSIRG MSIPL
SEL LEN
rw rw rs rw
RM0432
17 16
HSE HSE
RDY ON
r rw
1 0
MSI
MSION
RDY
r rw