ST STM32L4+ Series Reference Manual page 153

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Flash status register (FLASH_SR)

Address offset: 0x10

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:18 Reserved, must be kept at reset value.

Bits 13:10 Reserved, must be kept at reset value.

Bit 17 PEMPTY: Program EMPTY

Set by hardware on power-on reset or after OBL_LAUNCH command execution

if the Flash is not programmed and the user intends to boot from the main Flash.

Cleared by hardware on power-on reset or after OBL_LAUNCH command

execution if the Flash is programmed and the user intends to boot from main

Flash. This bit can also be set and cleared by software.

1: The bit value is toggling

0: No effect

This bit can be set to clear the Program Empty bit if an OBL_LAUNCH is done by

software after Flash programming (boot in main Flash selected). It finally forces

the boot in the main Flash, without loosing the debugger connection.

Bit 16 BSY: Busy

This indicates that a Flash operation is in progress. This is set on the beginning

of a Flash operation and reset when the operation finishes or when an error

Bit 15 OPTVERR: Option validity error

Set by hardware when the options read may not be the one configured by the

user. If option haven't been properly loaded, OPTVERR is set again after each

system reset.

Cleared by writing 1.

Bit 14 RDERR: PCROP read error

Set by hardware when an address to be read through the D-bus belongs to a

read protected area of the Flash (PCROP protection). An interrupt is generated if

RDERRIE is set in FLASH_CR.

Cleared by writing 1.

Bit 9 FASTERR: Fast programming error

Set by hardware when a fast programming sequence (activated by FSTPG) is

interrupted due to an error (alignment, size, write protection or data miss). The

corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at

the same time.

Cleared by writing 1.

RM0432 Rev 6

Embedded Flash memory (FLASH)

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