ST STM32L4+ Series Reference Manual page 443

RM0432
13.5.11 DMA2D background color register (DMA2D_BGCOLR)
Address offset: 0x0028
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 RED[7:0]: Red value
Bits 15:8 GREEN[7:0]: Green value
Bits 7:0 BLUE[7:0]: Blue value
13.5.12 DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR)
Address offset: 0x002C
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
GREEN[7:0]
rw rw rw rw
These bits define the red value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.
These bits define the green value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.
These bits define the blue value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Used also for fixed color FG in memory-to-memory with blending and fixed color FG
(BG fetch only with FG and BG PFC active) mode.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Chrom-ART Accelerator controller (DMA2D)
24 23 22
Res.
rw rw
8 7 6
rw rw rw
24 23 22
MA[31:16]
rw rw rw
8 7 6
MA[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
RED[7:0]
rw rw rw rw
5 4 3 2
BLUE[7:0]
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
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