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RM0432
Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx
25.5.4
PSSI interrupt enable register (PSSI_IER)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
The PSSI_IER register is used to enable interrupts. When one of the PSSI_IER bits is set,
the corresponding interrupt is enabled. This register is accessible both in read and write
modes.
Bits 31:2 Reserved, must be kept at reset value.
25.5.5
PSSI masked interrupt status register (PSSI_MIS)
This PSSI_MIS register is read-only. When read, it returns the current masked status value
of the corresponding interrupt (depending on the value in PSSI_IER). A bit in this register is
set if the corresponding enable bit in PSSI_IER is set and the corresponding bit in
PSSI_RIS is set.
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 1 OVR_IE: Data buffer overrun/underrun interrupt enable
0: No interrupt generation
1: An interrupt is generated if either an overrun or an underrun error occurred.
Bit 0 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
Res.
rw
17
16
Res.
Res.
1
0
Res.
r
801/2301
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