ST STM32L4+ Series Reference Manual page 962

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.12 Functional description: D-PHY management
The embedded MIPI
the DSI Wrapper.
A dedicated PLL and a dedicated 1.2 V regulator are also embedded to supply the clock
and the power supply to the DSI Host and D-PHY.
30.12.1 D-PHY configuration
The D-PHY configuration is carried out through the DSI Wrapper thanks to the DSI_WPCRx
registers.
Timing definition
The MIPI
timings are specified in nanoseconds (ns), it's mandatory to configure the Unit Interval Field
to ensure the good duration of all the timings.
Unit Interval is configure through the DSI_WPCR0.UIX4 field. This value defines the bit
period in High-Speed mode in unit of 0.25ns. If this period is not a multiple of 0.25 ns, the
value driven should be rounded down.
As an example, for a 300 Mbit/s link, the unit interval is 3.33 ns, so UIX4 shall be 13.33. In
this case a value of 13 (0x0D) should be written.
Slew-rate and delay tuning on pins
To fine tune DSI communication, slew-rates and delays be fine tuned:
•
slew-rate in High-Speed transmission on data lane and clock lane
•
slew-rate in Low-Power transmission on data lane and clock lane
•
transmission delay in High-Speed transmission on data land and clock lane
Slew-rate in High-Speed transmission
Slew-rate in Low-Power transmission
High-speed transmission delay
The default values for all this parameters is 2'h00. All this values can be programmed only
when the DSI is stopped (DSI_WCR.DSIEN = 0 and CR.EN = 0).
Low-power reception filter tuning
The cut-off frequency of the low-pass on Low-Power receiver can be fine tuned through the
LPRXFT field of the DSI_WPCR1 register. The default values is 2'h00 and it can be
programmed only when the DSI is stopped (CR.DSIEN = 0 and CR.EN = 0).
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D-PHY is control directly by the DSI Host and is configured through
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D-PHY manages all the communication timing with dedicated timers. As all the
Table 205. Slew-rate and delay tuning
Function Lane(s)
Clock lane
Data lanes
Clock lanes
Data lanes
Clock lane
Data lanes
RM0432 Rev 6
RM0432
Value field in DSI_WPCR1
HSTXSRCCL
HSTXSRCDL
LPSRCCL
LPSRCDL
HSTXDCL
HSTXDDL