ST STM32L4+ Series Reference Manual page 465

RM0432
14.5.8 Graphic MMU buffer 3 configuration register (GFXMMU_B3CR)
Address offset: 0x002C
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:23 PBBA[31:23]: Physical buffer base address
Bits 22:4 PBO[22:4]: Physical buffer offset
Bits 3:0 Reserved, must be kept at reset value.
14.5.9 Graphic MMU LUT entry x low (GFXMMU_LUTxL)
Address offset: 0x1000 + 8 * x, x = 0...1023
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
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Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 LVB[7:0]: Last Valid Block
Bits 15:8 FVB[7:0]: First Valid Block
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 EN: Enable
14.5.10 Graphic MMU LUT entry x high (GFXMMU_LUTxH)
Address offset: 0x1000 + 8 * x + 4, x = 0...1023
Reset value: 0x0000 0000
27 26 25
PBBA[31:23]
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11 10 9
PBO[15:4]
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Base address MSB of the physical buffer.
Offset of the physical buffer.
27 26 25
Res. Res. Res.
11 10 9
FVB[7:0]
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Number of the last valid block of line number X.
Number of the first valid block of line number x.
Line enable.
0: Line is disabled (no MMU evaluation is performed)
1: Line is enabled (MMU evaluation is performed)
24 23 22 21
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8 7 6 5
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24 23 22 21
Res.
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8 7 6 5
Res. Res. Res.
rw
RM0432 Rev 6
Chrom-GRC™ (GFXMMU)
20 19 18 17
PBO[22:16]
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4 3 2
Res. Res. Res.
rw
20 19 18 17
LVB[7:0]
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4 3 2
Res. Res. Res. Res.
16
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1 0
Res.
16
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1 0
EN
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