ST STM32L4+ Series Reference Manual page 124

Embedded Flash memory (FLASH)
Figure 5. Sequential 16-bit instructions execution (64-bit read data width)
@
1
Read ins 1, 2, 3, 4
@
1
Read ins 1, 2, 3, 4
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
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F D
WAIT
1 1
@ F
2 2
@
3
ins 1 ins 2
fetch fetch
Gives ins 1, 2, 3, 4
F D
WAIT
1 1
@ F
2 2
@
3
ins 1 ins 2
fetch fetch
Gives ins 1, 2, 3, 4
Read ins 5, 6, 7, 8
RM0432 Rev 6
E
1
D E
2 2
F D E
3 3 3
@ F D E
4 4 4 4
@
WAIT
5
@
6
ins 3 ins 4
fetch fetch
Read ins 5, 6, 7, 8
E
1
D E
2 2
F D E
3 3 3
@ F D E
4 4 4 4
@ F D E
5 5 5 5
@ F D
6 6 6
@ F
7 7
@
8
ins 3 ins 4 ins 5 ins 6
fetch fetch fetch fetch
Gives ins 5, 6, 7, 8
Read ins 9, 10, ...
WITHOUT PREFETCH
F D E
5 5 5
F D E
6 6 6
@ F D
7 7 7
@ F
8 8
ins 5 ins 6 ins 7 ins 8
fetch fetch fetch fetch
Gives ins 5, 6, 7, 8
WITH PREFETCH
E
6
D
7
Cortex-M4 pipeline
F
8
@ F
6 6
ins 7 ins 8
AHB protocol
fetch fetch
@: address requested
F: Fetch stage
D: Decode stage
E: Execute stage
RM0432
D E
6 6
MS33467V1