ST STM32L4+ Series Reference Manual page 946

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
Table 202
Period for which the DSI Host
keeps the link still
Period for which the DSI Host
keeps the link inactive
The values in these registers are measured in number of cycles of the Lane byte clock.
These registers are only used in Command mode because in Video mode, there is a rigid
timing schedule to be met to keep the display properly refreshed and it must not be broken
by these or any other timeouts. Setting a given timeout to 0 disables going into LP-11 state
and timeout for events of that category.
The read and the write requests in High-Speed mode are distinct from the read and the write
requests in Low-Power mode. For example, if HSRD_TOCNT is set to zero and
LPRD_TOCNT is set to a non-zero value, a generic read with no parameters does not
activate the PRESP_TO counter in High-Speed, but it activates the PRESP_TO in Low-
Power.
The DSI Host Timeout Counter Configuration Register 4 (DSI_TCCR3) includes a special
Presp mode (PM) bit to change the normal behavior of PRESP_TO in Adaptive Command
946/2301
Figure 217. Timing of PRESP_TO after a Write Request (HS or LP)
Host
LP-11
describes the fields used for the configuration of the PRESP_TO counter.
Table 202. PRESP_TO counter configuration
Description
After sending a
High-Speed read operation
After sending a
Low-Power read operation
After completing a
Bus-Turn-Around (BTA)
After sending a
High-Speed write operation
After sending a
Low-Power write operation
RM0432 Rev 6
Device
Device Ready
Register
DSI_TCCR1
DSI_TCCR2
DSI_TCCR5
DSI_TCCR3
DSI_TCCR4
RM0432
MSv35868V1
Field
HSRD_TOCNT
LPRD_TOCNT
BTA_TOCNT
HSWR_TOCNT
LPWR_TOCNT