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RM0432
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 DMAREQ_ID[6:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.
12.6.2
DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR)
Address offset: 0x080
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
SOF13
SOF12
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 SOF[13:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
12.6.3
DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR)
Address offset: 0x084
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
CSOF
CSOF
13
w
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 CSOF[13:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR
register.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
SOF11
SOF10
SOF9
r
r
r
28
27
26
25
Res.
Res.
Res.
12
11
10
9
CSOF
CSOF
CSOF
12
11
10
9
w
w
w
w
24
23
22
Res.
Res.
Res.
9
8
7
6
SOF8
SOF7
SOF6
r
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
CSOF
CSOF
CSOF
8
7
6
w
w
w
RM0432 Rev 6
DMA request multiplexer (DMAMUX)
21
20
19
Res.
Res.
Res.
5
4
3
SOF5
SOF4
SOF3
SOF2
r
r
r
21
20
19
Res.
Res.
Res.
Res.
5
4
3
CSOF
CSOF
CSOF
CSOF
5
4
3
w
w
w
18
17
16
Res.
Res.
Res.
2
1
0
SOF1
SOF0
r
r
r
18
17
16
Res.
Res.
2
1
0
CSOF
CSOF
2
1
0
w
w
w
411/2301
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