ST STM32L4+ Series Reference Manual page 322

Clock recovery system (CRS)
7.4 CRS functional description
7.4.1 CRS block diagram
OSC32_IN
OSC32_OUT
USB_DP
USB_DM
7.4.2 Synchronization input
The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can
be the signal from the LSE clock or the USB SOF signal. For a better robustness of the
SYNC input, a simple digital filter (2 out of 3 majority votes, sampled by the RC48 clock) is
implemented to filter out any glitches. This source signal also has a configurable polarity
and can then be divided by a programmable binary prescaler to obtain a synchronization
signal in a suitable frequency range (usually around 1 kHz).
For more information on the CRS synchronization source configuration, refer to
Section 7.7.2: CRS configuration register
It is also possible to generate a synchronization event by software, by setting the SWSYNC
bit in the CRS_CR register.
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Figure 23. CRS block diagram
CRS_SYNC
GPIO
LSE
USB
RCC
SYNCSRC
TRIM
RC 48 MHz
HSI48
(CRS_CFGR).
RM0432 Rev 6
SWSYNC
SYNC divider
(/1, /2, /4,..., /128)
FELIM
FEDIR FECAP
16-bit counter
RELOAD
To peripherals
RM0432
SYNC
MS52498V1