ST STM32L4+ Series Reference Manual page 977

RM0432
30.14.6 Configuring the video mode
The video mode configuration shall defines the behavior of the controller in Low-power for
command transmission, the type of video transmission (burst or non-burst mode) and the
panel horizontal and vertical timing:
•
Select the video transmission mode to define how the processor requires the video line
to be transported through the DSI link.
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–
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•
Select the video mode type
–
–
•
Define the video horizontal timing configuration as follows:
–
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
Configure the Low-Power transitions in the DSI_VMCR to define the video periods
which are permitted to go to Low-Power if there is time available to do so.
Configure if the controller should request the peripheral acknowledge message at
the end of frames (DSI_VMCR.FBTAAE).
Configure if commands are to be transmitted in Low-Power (DSI_VMCR.LPE).
Burst mode:
Configure the video mode type (DSI_VMCR.VMT) with value 2'b1x.
Configure the video packet size (DSI_VPCR.VPSIZE) with the size of the active
line period, measured in pixels.
The registers DSI_VCCR and DSI_VNPCR are ignored by the DSI Host.
Non-Burst mode:
Configure the video mode type (DSI_VMCR.VMT) with 2'b00 to enable the
transmission of sync pulses or with 2'b01 to enable the transmission of sync
events.
Configure the video packet size (DSI_VPCR.VPSIZE) with the number of pixels to
be transmitted in a single packet. Selecting this value depends on the available
memory of the attached peripheral, if the data is first stored, or on the memory you
want to select for the FIFO in DSI Host.
Configure the number of chunks (DSI_VCCR.NUMC) with the number of packets
to be transmitted per video line. The value of VPSIZE * NUMC is the number of
pixels per line of video, except if NUMC is 0, which disables the multi-packets. If
you set it to 1, there is still only one packet per line, but it can be part of a chunk,
followed by a null packet.
Configure the null packet size (DSI_VNPCR.NPSIZE) with the size of null packets
to be inserted as part of the chunks. Setting it to 0 disables null packets.
Configure the horizontal line time (DSI_VLCR.HLINE) with the time taken by a
LTDC video line measured in cycles of lane byte clock (for a clock lane at 500 MHz
the lane byte clock period is 8 ns). When the periods of LTDC clock and lane byte
clock are not multiples, the value to program the DSI_VLCR.HLINE needs to be
rounded. A timing mismatch is introduced between the lines due to the rounding of
configuration values. If the DSI Host is configured not to go to Low-Power, this
timing divergence accumulates on every line, introducing a significant amount of
mismatch towards the end of the frame. The reason for this is that the DSI Host
cannot re-synchronize on every new line because it transmits the blanking packets
when the Horizontal Sync event occurs on the LTDC interface. However, the
accumulated mismatch should become extinct on the last line of a frame, where,
according to the DSI specification, the link should always return to Low-Power
regaining synchronization, when a new frame starts on a vertical sync event. If the
accumulated timing mismatch is greater than the time in Low-Power on the last
RM0432 Rev 6 977/2301
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