ST STM32L4+ Series Reference Manual page 913

RM0432
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 WHSPPOS[11:0]: window horizontal stop position
These bits configure the last visible pixel of a line of the layer window.
WHSPPOS[11:0] must be ≥ AHBP[11:0] bits + 1 (programmed in LTDC_BPCR register).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 WHSTPOS[11:0]: window horizontal start position
These bits configure the first visible pixel of a line of the layer window.
WHSTPOS[11:0] must be ≤ AAW[11:0] bits (programmed in LTDC_AWCR register).
Example:
The LTDC_BPCR register is configured to 0x000E0005 (AHBP[11:0] is 0xE) and the
LTDC_AWCR register is configured to 0x028E01E5 (AAW[11:0] is 0x28E). To configure the
horizontal position of a window size of 630x460, with horizontal start offset of 5 pixels in the
active data area:
1. layer window first pixel, WHSTPOS[11:0], must be programmed to 0x14 (0xE+1+0x5)
2. layer window last pixel, WHSPPOS[11:0], must be programmed to 0x28A.
29.8.16 LTDC layer x window vertical position configuration register
(LTDC_LxWVPCR)
This register defines the vertical position (first and last line) of the layer1 or 2 window.
The first visible line of a frame is the programmed value of AVBP[10:0] bits + 1 in the register
LTDC_BPCR register.
The last visible line of a frame is the programmed value of AAH[10:0] bits in the
LTDC_AWCR register.
Address offset: 0x8C + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:16 WVSPPOS[10:0]: window vertical stop position
These bits configure the last visible line of the layer window.
WVSPPOS[10:0] must be ≥ AVBP[10:0] bits + 1 (programmed in LTDC_BPCR register).
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 WVSTPOS[10:0]: window vertical start position
These bits configure the first visible line of the layer window.
WVSTPOS[10:0] must be ≤ AAH[10:0] bits (programmed in LTDC_AWCR register).
27 26 25 24
Res.
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11 10 9 8
Res.
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RM0432 Rev 6
LCD-TFT display controller (LTDC)
23 22 21 20
WVSPPOS[10:0]
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7 6 5 4
WVSTPOS[10:0]
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19 18 17 16
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3 2 1 0
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