ST STM32L4+ Series Reference Manual page 769

RM0432
Table 155. Positioning of captured data bytes in 32-bit words (8-bit width)
Byte address
0
4
10-bit data
When EDM[1:0] = 01 in DCMI_CR, the camera interface captures 10-bit data at its input
DCMI_D[9:0] and stores them as the 10 least significant bits of a 16-bit word. The remaining
most significant bits of the DCMI_DR register (bits 11 to 15) are cleared to zero. So, in this
case, a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in the table below.
Table 156. Positioning of captured data bytes in 32-bit words (10-bit width)
Byte address
0
4
12-bit data
When EDM[1:0] = 10 in DCMI_CR, the camera interface captures the 12-bit data at its input
DCMI_D[11:0] and stores them as the 12 least significant bits of a 16-bit word. The
remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is
made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in the table below.
Table 157. Positioning of captured data bytes in 32-bit words (12-bit width)
Byte address
0
4
14-bit data
When EDM[1:0] = 11 in DCMI_CR, the camera interface captures the 14-bit data at its input
DCMI_D[13:0] and stores them as the 14 least significant bits of a 16-bit word. The
remaining most significant bits are cleared to zero. So, in this case a 32-bit data word is
made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in the table below.
31:24 23:16
D [7:0] D
n+3 n+2
D [7:0] D
n+7 n+6
31:26 25:16
0 D
n+1
0 D
n+3
31:28 27:16
0 D
n+1
0 D
n+3
RM0432 Rev 6
Digital camera interface (DCMI)
15:8
[7:0] D [7:0]
n+1
[7:0] D [7:0]
n+5
15:10
[9:0] 0
[9:0] 0
15:12
[11:0] 0
[11:0] 0
7:0
D [7:0]
n
D [7:0]
n+4
nd
9:0
D [9:0]
n
D [9:0]
n+2
nd
11:0
D [11:0]
n
D [11:0]
n+2
nd
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