ST STM32L4+ Series Reference Manual page 589

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Bit 3 SMF: Status match flag

This bit is set in Automatic-polling mode when the unmasked received data matches the

corresponding bits in the match register (OCTOSPI_PSMAR).

It is cleared by writing 1 to CSMF.

Bit 2 FTF: FIFO threshold flag

In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any

data left in the FIFO after the reads from the external device are complete.

It is cleared automatically as soon as the threshold condition is no longer true.

In Automatic-polling mode this bit is set every time the status register is read, and the bit is

cleared when the data register is read.

Bit 1 TCF: Transfer complete flag

This bit is set in Indirect mode when the programmed number of data has been transferred or

in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF.

Bit 0 TEF: Transfer error flag

This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode.

It is cleared by writing 1 to CTEF.

OCTOSPI flag clear register (OCTOSPI_FCR)

Address offset: 0x0024

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CTOF: Clear timeout flag

Writing 1 clears the TOF flag in the OCTOSPI_SR register.

Bit 3 CSMF: Clear status match flag

Writing 1 clears the SMF flag in the OCTOSPI_SR register.

Bit 2 Reserved, must be kept at reset value.

Bit 1 CTCF: Clear transfer complete flag

Writing 1 clears the TCF flag in the OCTOSPI_SR register.

Bit 0 CTEF: Clear transfer error flag

Writing 1 clears the TEF flag in the OCTOSPI_SR register.

RM0432 Rev 6

Octo-SPI interface (OCTOSPI)

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