Advertisement
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.15.39 DSI Host PHY TX Triggers Configuration Register (DSI_PTTCR)
Address offset: 0x00AC
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31: 4 Reserved, must be kept at reset value
Bits 3: 0 TX_TRIG: Transmission Trigger
30.15.40 DSI Host PHY Status Register (DSI_PSR)
Address offset: 0x00B0
Reset value: 0x0000 1528
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31: 9 Reserved, must be kept at reset value
Bit 8 UAN1: ULPS Active Not lane 1
Bit 7 PSS1: PHY Stop State lane 1
Bit 6 RUE0: RX ULPS Escape lane 0
Bit 5 UAN0: ULPS Active Not lane 1
Bit 4 PSS0: PHY Stop State lane 0
Bit 3 UANC: ULPS Active Not Clock lane
1008/2301
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
Escape mode Transmit Trigger 0-3.
Only one bit of TX_TRIG is asserted at any given time.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit indicates the status of ulpsactivenot1lane D-PHY signal.
This bit indicates the status of phystopstate1lane D-PHY signal.
This bit indicates the status of rxulpsesc0lane D-PHY signal.
This bit indicates the status of ulpsactivenot0lane D-PHY signal.
This bit indicates the status of phystopstate0lane D-PHY signal.
This bit indicates the status of ulpsactivenotclklane D-PHY signal.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
UAN1
PSS1
RUE0
UAN0
ro
ro
ro
RM0432 Rev 6
20
19
18
Res.
Res.
Res.
4
3
2
Res.
TX_TRIG[3:0]
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PSS0
UANC
PSSC
ro
ro
ro
ro
RM0432
17
16
Res.
Res.
1
0
rw
17
16
Res.
Res.
1
0
PD
Res.
ro
Advertisement
Need help?
Do you have a question about the STM32L4+ Series and is the answer not in the manual?