ST STM32L4+ Series Reference Manual page 210

Power control (PWR)
Stop 1 mode
Mode entry
Mode exit
Wakeup latency
5.3.8 Stop 2 mode
The Stop 2 mode is based on the Cortex
clock gating. In Stop 2 mode, all clocks in the V
the HSI16 and the HSE oscillators are disabled. Some peripherals with wakeup capability
(I2C3 and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16
after receiving the frame if it is not a wakeup frame. In this case the HSI16 clock is
propagated only to the peripheral requesting it.
SRAM1, SRAM2, SRAM3 and register contents are preserved. The SRAM3 content is
preserved or lost following the RRSTP bit configuration in the PWR_CR1 register. By
default, after reset, the RRSTP bit is reset thus the SRAM3 content is lost during Stop 2.
The BOR is always available in Stop 2 mode. The consumption is increased when
thresholds higher than V
210/2301
Table 32. Stop 1 mode
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = "001" in PWR_CR1
On Return from ISR while:
– SLEEPDEEP bit is set in Cortex
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = "001" in PWR_CR1
Note: To enter Stop 1 mode, all EXTI Line pending bits (in
register 1 (EXTI_PR1)), and the peripheral flags generating wakeup
interrupts must be cleared. Otherwise, the Stop 1 mode entry
procedure is ignored and program execution continues.
If WFI or Return from ISR was used for entry
Any EXTI Line configured in interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 76: STM32L4Rxxx and STM32L4Sxxx vector
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in event mode. Refer to
Wakeup event management.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer
toTable 76: STM32L4Rxxx and STM32L4Sxxx vector
Wakeup event: refer to
Longest wakeup time between: MSI or HSI16 wakeup time and regulator
wakeup time from Low-power mode + Flash wakeup time from Stop 1
mode.
®
-M4 Deepsleep mode combined with peripheral
are used.
BOR0
RM0432 Rev 6
Description
®
-M4 System Control register
®
-M4 System Control register
Section 16.3.2: Wakeup event management
domain are stopped, the PLL, the MSI,
CORE
RM0432
Pending
table.
Section 16.3.2:
table.