ST STM32L4+ Series Reference Manual page 634

Analog-to-digital converters (ADC)
Note: The regular trigger selection cannot be changed on-the-fly.
The injected trigger selection can be anticipated and changed on-the-fly. Refer to
Section 21.4.21: Queue of context for injected conversions on page 638
Each ADC master shares the same input triggers with its ADC slave as described in
Figure 99.
Regular
sequencer
triggers
Injected
sequencer
triggers
Table 130
and injected conversion.
Name
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
EXT8
EXT9
634/2301
Figure 99. Triggers sharing between ADC master and ADC slave
EXT0
EXT1
....... .......
EXT15
JEXT0
JEXT1
....... .......
JEXT15
to Table 131 give all the possible external triggers of the three ADCs for regular
Table 130. ADC1 - External triggers for regular channels
Source
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM2_CH2
TIM3_TRGO
TIM4_CH4
EXTI line 11
TIM8_TRGO
TIM8_TRGO2
TIM1_TRGO
ADC MASTER
EXTSEL[3:0]
ADC SLAVE
EXTSEL[3:0]
Type
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
External pin
Internal signal from on-chip timers
Internal signal from on-chip timers
Internal signal from on-chip timers
RM0432 Rev 6
External regular trigger
External injected trigger
JEXTSEL[3:0]
External regular trigger
External injected trigger
JEXTSEL[3:0]
EXTSEL[3:0]
RM0432
MS35356V1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001