ST STM32L4+ Series Reference Manual page 903

RM0432
29.8 LTDC registers
29.8.1 LTDC synchronization size configuration register (LTDC_SSCR)
This register defines the number of horizontal synchronization pixels minus 1 and the
number of vertical synchronization lines minus 1. Refer to
LTDC programmable parameters
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HSW[11:0]: horizontal synchronization width (in units of pixel clock period)
These bits define the number of Horizontal Synchronization pixel minus 1.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 VSH[10:0]: vertical synchronization height (in units of horizontal scan line)
These bits define the vertical Synchronization height minus 1. It represents the number of
horizontal synchronization lines.
29.8.2 LTDC back porch configuration register (LTDC_BPCR)
This register defines the accumulated number of horizontal synchronization and back porch
pixels minus 1 (HSYNC width + HBP - 1) and the accumulated number of vertical
synchronization and back porch lines minus 1 (VSYNC height + VBP - 1). Refer to
Figure 200
configuration.
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
27 26 25
rw rw rw
11 10 9
Res.
rw rw
and Section 29.5: LTDC programmable parameters
27 26 25
rw rw rw
11 10 9
Res.
rw rw
RM0432 Rev 6
LCD-TFT display controller (LTDC)
for an example of configuration.
24 23 22 21
HSW[11:0]
rw rw rw rw
8 7 6 5
VSH[10:0]
rw rw rw rw
24 23 22 21
AHBP[11:0]
rw rw rw rw
8 7 6 5
AVBP[10:0]
rw rw rw rw
Figure 200 and Section 29.5:
20 19 18
rw rw rw
4 3 2
rw rw rw
for an example of
20 19 18
rw rw rw
4 3 2
rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
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