ST STM32L4+ Series Reference Manual page 444

Chrom-ART Accelerator controller (DMA2D)
Bits 31:0 MA[31:0]: Memory Address
13.5.13 DMA2D background CLUT memory address register
(DMA2D_BGCMAR)
Address offset: 0x0030
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 MA[31:0]: Memory address
13.5.14 DMA2D output PFC control register (DMA2D_OPFCCR)
Address offset: 0x0034
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
444/2301
Address of the data used for the CLUT address dedicated to the foreground image. This
register can only be written when no transfer is ongoing. Once the CLUT transfer has
started, this register is read-only.
If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Address of the data used for the CLUT address dedicated to the background image.
This register can only be written when no transfer is on going. Once the CLUT transfer
has started, this register is read-only.
If the background CLUT format is 32-bit, the address must be 32-bit aligned.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. SB
rw
24 23 22
MA[31:16]
rw rw rw
8 7 6
MA[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
RBS AI Res. Res.
rw rw
5 4 3 2
Res. Res. Res.
rw
RM0432
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
CM[2:0]
rw rw