ST STM32L4+ Series Reference Manual page 509

RM0432
Bit number
6
5:4
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Table 93. FMC_BCRx bitfields (mode 1) (continued)
Bit name
FACCEN Don't care
MWID As needed
MTYP As needed, exclude 0x2 (NOR Flash memory)
MUXE 0x0
MBKEN 0x1
Table 94. FMC_BTRx bitfields (mode 1)
Bit name
Duration of the data hold phase (DATAHLD HCLK cycles for read
DATAHLD
accesses, DATAHLD+1 HCLK cycles for write accesses).
ACCMOD Don't care
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
DATAST Duration of the second access phase (DATAST HCLK cycles).
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET
Minimum value for ADDSET is 0.
RM0432 Rev 6
Flexible static memory controller (FSMC)
Value to set
Value to set
509/2301
554