ST STM32L4+ Series Reference Manual page 975

RM0432
Configuring the D-PHY parameters in the DSI wrapper
The DSI wrapper can be used to fine tunes either timing or physical parameters of the D-
PHY. This operation is not required for a standard usage of the D-PHY. All the fields and
parameters are described in the register description of the DSI wrapper.
Only one filed is mandatory to properly start the D-PHY: the Unit Interval multiplied by 4
(UIX4) field of the DSI wrapper PHY Configuration Register 1 (DSI_WPCR0).
This field defines the bit period in High-Speed mode in unit of 0.25 ns, and is used as a
timebase for all the timings managed by the D-PHY.
If the link is working at 600Mbit/s, the unit interval shall be 1.667 ns, i.e 6.667 ns when
multiplied by four. When rounded down, a value of 6 must be written in the UIX4 field of the
DSI_WPCR0 register.
Configuring the D-PHY parameters in the DSI host
The DSI Host stores the configuration of D-PHY timing parameters and number of lanes.
The following fields must be configured prior to any startup:
•
Number of data lanes in the DSI_PCONFR register
•
Automatic clock lane control (ACR) in the DSI_CLCR register
•
Clock control (DPCC) in the DSI_CLCR register
•
Time for LP/HS and HS/LP transitions for both clock lane and data lanes in
DSI_CLTCR and DSI_DLTCR registers
•
Stop wait time in the DSI_PCONFR register
30.14.3 Configuring the DSI host timing
All the protocol timing shall be configured in the DSI host.
Clock divider configuration
Two clocks are generated internally
• Timeout Clock;
•
TX Escape Clock.
The timeout clock is used as the timing unit in the configuration of HS to LP and LP to HS
transition error. It's division factor is configured by the Timeout Clock Division (TOCKDIV)
field of the DSI Host Clock Control Register (DSI_CCR).
The TX Escape clock is used in Low-Power transmission. Its division factor is configured by
the TX Escape Clock Division (TXECKDIV) field of the DSI Host Clock Control Register
(DSI_CCR) relatively to the lanebyteclock. It's typical value shall be around 20MHz.
Timeout configuration
The timings for timeout management as described in
Host Timeout Counter Configuration Registers (DSI_TCCR0 to DSI_TCCR5).
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
RM0432 Rev 6
Section 30.8 are configured in the DSI
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