ST STM32L4+ Series Reference Manual page 562

Octo-SPI interface (OCTOSPI)
Figure 72. DTR read in Octal mode with DQS (Macronix mode) example
CS#
CLK
DQS
IO[7:0]
19.4.4 OCTOSPI Regular-command mode signal interface
Single-SPI mode
The legacy SPI mode allows just a single bit to be sent/received serially. In this mode, the
data is sent to the external device over the SO signal (whose I/O are shared with IO0). The
data received from the external device arrives via SI (whose I/O are shared with IO1).
The different phases can each be configured separately to use this Single-bit mode by
setting to 001 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and
OCTOSPI_WCCR).
In each phase configured in Single-SPI mode:
• IO0 (SO) is in output mode.
•
IO1 (SI) is in input mode (high impedance).
• IO2 is in output mode and forced to 0 (to deactivate the "write protect" function).
•
IO3 is in output mode and forced to 1 (to deactivate the "hold" function).
• IO4/IO5/IO6/IO7 are in output mode and forced to 0.
This is the case even for the dummy phase if DMODE[2:0] = 001.
Dual-SPI mode
In Dual-SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.
The different phases can each be configured separately to use Dual-SPI mode by setting
to 010 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and
OCTOSPI_WCCR).
In each phase configured in Dual-SPI mode:
•
IO0/IO1 are at high-impedance (input) during the data phase for the read operations,
and outputs in all other cases.
• IO2 is in output mode and forced to 0.
•
IO3 is in output mode and forced to 1.
• IO4/IO5/IO6/IO7 are in output mode and forced to 0.
In the dummy phase when DMODE[2:0] = 010, IO0/IO1 are always high-impedance.
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EEh 11h
A[31:24] A[23:16] A[15:8] A[7:0]
Address
RM0432 Rev 6
D1 D0
Word
Dummy
unit
RM0432
D3 D2
Word
unit
MSv43489V1