ST STM32L4+ Series Reference Manual page 267

RM0432
• f(PLLSAI1_R) = f(VCOSAI1 clock) / PLLSAI1R
31 30 29
PLLSAI1PDIV[4:0]
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15 14 13
Res.
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Bits 31:27 PLLSAI1PDIV[4:0]: PLLSAI1 division factor for PLLSAI1CLK
Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI1CLK output
clock frequency = VCOSAI1 frequency / PLLSAI1PDIV.
Note:
Bits 26:25 PLLSAI1R[1:0]: PLLSAI1 division factor for PLLADC1CLK (ADC clock)
Bit 24 PLLSAI1REN: PLLSAI1 PLLADC1CLK output enable
Bit 23 Reserved, must be kept at reset value.
Bits 22:21 PLLSAI1Q[1:0]: PLLSAI1 division factor for PLL48M2CLK (48 MHz clock)
Caution:
28 27 26 25
PLLSAI1R[1:0]
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12 11 10 9
PLLSAI1N[6:0]
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00000: PLLSAI1CLK is controlled by the bit PLLSAI1P
00001: Reserved.
00010: PLLSAI1CLK = VCOSAI1 / 2
....
11111: PLLSAI1CLK = VCOSAI1 / 31
This bit can be written only when the PLLSAI1 is disabled.
Set and cleared by software to control the frequency of the PLLSAI1 output clock
PLLADC1CLK. This output can be selected as ADC clock. These bits can be written only if
PLLSAI1 is disabled.
PLLADC1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1R with PLLSAI1R =
2, 4, 6, or 8
00: PLLSAI1R = 2
01: PLLSAI1R = 4
10: PLLSAI1R = 6
11: PLLSAI1R = 8
Set and reset by software to enable the PLLADC1CLK output of the PLLSAI1 (used as clock
for ADC).
In order to save power, when the PLLADC1CLK output of the PLLSAI1 is not used, the value
of PLLSAI1REN should be 0.
0: PLLADC1CLK output disable
1: PLLADC1CLK output enable
Set and cleared by software to control the frequency of the PLLSAI1 output clock
PLL48M2CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if PLLSAI1 is disabled.
PLL48M2CLK output clock frequency = VCOSAI1 frequency / PLLSAI1Q with PLLSAI1Q =
2, 4, 6, or 8
00: PLLSAI1Q = 2
01: PLLSAI1Q = 4
10: PLLSAI1Q = 6
11: PLLSAI1Q = 8
The software has to set these bits correctly not to exceed 120 MHz on
this domain.
24 23 22
PLLSAI
Res. PLLSAI1Q[1:0]
1REN
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8 7 6
PLLSAI1M[3:0]
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RM0432 Rev 6
Reset and clock control (RCC)
21 20 19 18
PLLSAI
Res. Res.
1QEN
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5 4 3 2
Res. Res.
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17 16
PLLSAI PLLSAI
1P 1PEN
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1 0
Res. Res.
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