ST STM32L4+ Series Reference Manual page 786

Digital camera interface (DCMI)
24.5.8 DCMI embedded synchronization unmask register (DCMI_ESUR)
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:24 FEU[7:0]: Frame end delimiter unmask
Bits 23:16 LEU[7:0]: Line end delimiter unmask
Bits 15:8 LSU[7:0]: Line start delimiter unmask
Bits 7:0 FSU[7:0]: Frame start delimiter unmask
24.5.9 DCMI crop window start (DCMI_CWSTRT)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
Res. Res.
rw
786/2301
28 27 26 25
FEU[7:0]
rw rw rw rw
12 11 10 9
LSU[7:0]
rw rw rw rw
This byte specifies the mask to be applied to the code of the frame end delimiter.
0: The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the
frame end delimiter with the received data.
1: The corresponding bit in the FEC byte in DCMI_ESCR is compared while comparing the
frame end delimiter with the received data.
This byte specifies the mask to be applied to the code of the line end delimiter.
0: The corresponding bit in the LEC byte in DCMI_ESCR is masked while comparing the line
end delimiter with the received data.
1: The corresponding bit in the LEC byte in DCMI_ESCR is compared while comparing the
line end delimiter with the received data.
This byte specifies the mask to be applied to the code of the line start delimiter.
0: The corresponding bit in the LSC byte in DCMI_ESCR is masked while comparing the line
start delimiter with the received data.
1: The corresponding bit in the LSC byte in DCMI_ESCR is compared while comparing the
line start delimiter with the received data.
This byte specifies the mask to be applied to the code of the frame start delimiter.
0: The corresponding bit in the FSC byte in DCMI_ESCR is masked while comparing the
frame start delimiter with the received data.
1: The corresponding bit in the FSC byte in DCMI_ESCR is compared while comparing the
frame start delimiter with the received data.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
24 23 22
rw rw rw
8 7 6
rw rw rw
24 23 22
VST[12:0]
rw rw rw
8 7 6
HOFFCNT[13:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
LEU[7:0]
rw rw rw rw
5 4 3 2
FSU[7:0]
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0432
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw