ST STM32L4+ Series Reference Manual page 327

RM0432
Bit 4 Reserved, must be kept at reset value.
Bit 3 ESYNCIE: Expected SYNC interrupt enable
Bit 2 ERRIE: Synchronization or trimming error interrupt enable
Bit 1 SYNCWARNIE: SYNC warning interrupt enable
Bit 0 SYNCOKIE: SYNC event OK interrupt enable
7.7.2 CRS configuration register (CRS_CFGR)
This register can be written only when the frequency error counter is disabled (CEN bit is
cleared in CRS_CR). When the counter is enabled, this register is write-protected.
Address offset: 0x04
Reset value: 0x2022 BB7F
31 30 29
SYNCPOL Res. SYNCSRC[1:0]
rw rw
15 14 13
rw rw rw
Bit 31 SYNCPOL: SYNC polarity selection
Bit 30 Reserved, must be kept at reset value.
Bits 29:28 SYNCSRC[1:0]: SYNC signal source selection
Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
Bit 27 Reserved, must be kept at reset value.
0: Expected SYNC (ESYNCF) interrupt disabled
1: Expected SYNC (ESYNCF) interrupt enabled
0: Synchronization or trimming error (ERRF) interrupt disabled
1: Synchronization or trimming error (ERRF) interrupt enabled
0: SYNC warning (SYNCWARNF) interrupt disabled
1: SYNC warning (SYNCWARNF) interrupt enabled
0: SYNC event OK (SYNCOKF) interrupt disabled
1: SYNC event OK (SYNCOKF) interrupt enabled
28 27 26
Res. SYNCDIV[2:0]
rw rw
12 11 10
rw rw rw
This bit is set and cleared by software to select the input polarity for the SYNC signal source.
0: SYNC active on rising edge (default)
1: SYNC active on falling edge
These bits are set and cleared by software to select the SYNC signal source.
00: GPIO selected as SYNC signal source
01: LSE selected as SYNC signal source
10: USB SOF selected as SYNC signal source (default).
11: Reserved
periodic USB SOF is not generated by the host. No SYNC signal is therefore provided
to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock
precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
should be used as SYNC signal.
25 24 23 22
rw rw rw rw
9 8 7 6
RELOAD[15:0]
rw rw rw rw
RM0432 Rev 6
Clock recovery system (CRS)
21 20 19 18
FELIM[7:0]
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
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