ST STM32L4+ Series Reference Manual page 548

Flexible static memory controller (FSMC)
Bits 12:9 TCLR[3:0]: CLE to RE delay
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 ECCEN: ECC computation logic enable bit
Bits 5:4 PWID[1:0]: Data bus width
Bit 3 PTYP: Memory type
Bit 2 PBKEN: NAND Flash memory bank enable bit
Bit 1 PWAITEN: Wait feature enable bit
Bit 0 Reserved, must be kept at reset value.
548/2301
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Defines the external memory device width.
00: 8 bits
01: 16 bits (default after reset).
10: reserved.
11: reserved.
Defines the type of device attached to the corresponding memory bank:
0: Reserved, must be kept at reset value
1: NAND Flash (default after reset)
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB
bus
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
Enables the Wait feature for the NAND Flash memory bank:
0: disabled
1: enabled
RM0432 Rev 6
RM0432