ST STM32L4+ Series Reference Manual page 594

Octo-SPI interface (OCTOSPI)
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 ADSIZE[1:0]: Address size
This field defines address size.
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
This field can be written only when BUSY = 0.
Bit 11 ADDTR: Address double transfer rate
This bit sets the DTR mode for the address phase.
0: DTR mode disabled for address phase
1: DTR mode enabled for address phase
This field can be written only when BUSY = 0.
Bits 10:8 ADMODE[2:0]: Address mode
This field defines the Address phase's mode of operation.
000: No address
001: Address on a single line
010: Address on two lines
011: Address on four lines
100: Address on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 ISIZE[1:0]: Instruction size
This bit defines instruction size.
00: 8-bit instruction
01: 16-bit instruction
10: 24-bit instruction
11: 32-bit instruction
This field can be written only when BUSY = 0.
Bit 3 IDTR: Instruction double transfer rate
This bit sets the DTR mode for the instruction phase.
0: DTR mode disabled for instruction phase
1: DTR mode enabled for instruction phase
This field can be written only when BUSY = 0.
Bits 2:0 IMODE[2:0]: Instruction mode
This field defines the Instruction phase's mode of operation.
000: No instruction
001: Instruction on a single line
010: Instruction on two lines
011: Instruction on four lines
100: Instruction on eight lines
101-111: Reserved
This field can be written only when BUSY = 0.
594/2301 RM0432 Rev 6
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