ST STM32L4+ Series Reference Manual page 904

LCD-TFT display controller (LTDC)
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 AHBP[11:0]: accumulated horizontal back porch (in units of pixel clock period)
These bits define the accumulated horizontal back porch width that includes the horizontal
synchronization and horizontal back porch pixels minus 1.
The horizontal back porch is the period between horizontal synchronization going inactive
and the start of the active display part of the next scan line.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 AVBP[10:0]: accumulated Vertical back porch (in units of horizontal scan line)
These bits define the accumulated vertical back porch width that includes the vertical
synchronization and vertical back porch lines minus 1.
The vertical back porch is the number of horizontal scan lines at a start of frame to the start of
the first active scan line of the next frame.
29.8.3 LTDC active width configuration register (LTDC_AWCR)
This register defines the accumulated number of horizontal synchronization, back porch and
active pixels minus 1 (HSYNC width + HBP + active width - 1) and the accumulated number
of vertical synchronization, back porch lines and active lines minus 1
(VSYNC height + BVBP + active height - 1). Refer to
programmable parameters
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 AAW[11:0]: accumulated active width (in units of pixel clock period)
These bits define the accumulated active width which includes the horizontal
synchronization, horizontal back porch and active pixels minus 1.
The active width is the number of pixels in active display area of the panel scan line.
Refer to device datasheet for maximum active width supported following maximum pixel
clock.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 AAH[10:0]: accumulated active height (in units of horizontal scan line)
These bits define the accumulated height which includes the vertical synchronization, vertical
back porch and the active height lines minus 1. The active height is the number of active
lines in the panel.
Refer to device datasheet for maximum active height supported following maximum pixel
clock.
904/2301
for an example of configuration.
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Res.
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RM0432 Rev 6
Figure 200
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AAW[11:0]
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AAH[10:0]
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RM0432
and Section 29.5: LTDC
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