ST STM32L4+ Series Reference Manual page 1015

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Bit 5 PSEIE: Packet Size Error Interrupt Enable

Bit 4 CRCEIE: CRC Error Interrupt Enable

Bit 3 ECCMEIE: ECC Multi-bit Error Interrupt Enable

Bit 2 ECCSEIE: ECC Single-bit Error Interrupt Enable

Bit 1 TOLPRXIE: Timeout Low-Power Reception Interrupt Enable

Bit 0 TOHSTXIE: Timeout High-Speed Transmission Interrupt Enable

30.15.45 DSI Host Force Interrupt Register 0 (DSI_FIR0)

Address offset: 0x00D8

Reset value: 0x0000 0000

Bits 31: 21 Reserved, must be kept at reset value

Bit 20 FPE4: Force PHY Error 4

Bit 19 FPE3: Force PHY Error 3

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only

This bit enables the interrupt generation on Packet Size Error.

0: Interrupt on Packet Size Error disabled.

1: Interrupt on Packet Size Error enabled.

This bit enables the interrupt generation on CRC Error.

0: Interrupt on CRC Error disabled.

1: Interrupt on CRC Error enabled.

This bit enables the interrupt generation on ECC Multi-bit Error.

0: Interrupt on ECC Multi-bit Error disabled.

1: Interrupt on ECC Multi-bit Error enabled.

This bit enables the interrupt generation on ECC Single-bit Error.

0: Interrupt on ECC Single-bit Error disabled.

1: Interrupt on ECC Single-bit Error enabled.

This bit enables the interrupt generation on Timeout Low-Power Reception.

0: Interrupt on Timeout Low-Power Reception disabled.

1: Interrupt on Timeout Low-Power Reception enabled.

This bit enables the interrupt generation on Timeout High-Speed Transmission .

0: Interrupt on Timeout High-Speed Transmission disabled.

1: Interrupt on Timeout High-Speed Transmission enabled.

Writing one to this bit forces a PHY Error 4.

Writing one to this bit forces a PHY Error 3.

RM0432 Rev 6

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