ST STM32L4+ Series Reference Manual page 183

RM0432
When V
When V
V
REF+
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
–
–
VREF- and VREF+ pins are not available on all packages. When not available on the
package, they are bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disable (refer to related device
datasheet for packages pinout description).
V
REF-
An embedded linear voltage regulator is used to supply the internal digital power V
V is the power supply for digital peripherals and memories.
CORE
Figure 9. STM32L4P5xx/Q5xx, STM32L4S5xx/R5xx and STM32L4S7xx/L4R7xx
< 2 V, V must be equal to V
DDA REF+
≥ 2 V, V must be between 2 V and V
DDA REF+
can be grounded when ADC and DAC are not active.
V around 2.048 V. This requires V
REF+
V around 2.5 V. This requires V
REF+
must always be equal to V
V
DDA
V
SSA
V
DDUSB
V
SS
V
DDIO2
V
SS
V
SS
V
DD
2 x V
DD12
V
BAT
.
DDA
equal to or higher than 2.4 V.
DDA
equal to or higher than 2.8 V.
DDA
.
SSA
power supply overview
V domain
DDA
1 x A/D converter
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
USB transceivers
V domain
DDIO2
V
DDIO2
I/O ring
PG[15:2]
V domain
DD
V
DDIO1
I/O ring
Reset block
Temp. sensor
3 x PLL, HSI, MSI
Standby circuitry
(Wakeup logic,
IWDG)
V
Voltage regulator
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
RM0432 Rev 6
Power control (PWR)
.
DDA
V domain
CORE
Core
SRAM1
SRAM2
SRAM3
Digital
peripherals
CORE
Flash memory
.
CORE
MSv43404V2
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