ST STM32L4+ Series Reference Manual page 568

Octo-SPI interface (OCTOSPI)
Read and write operation with additional latency
If the device needs an additional latency (during refresh period of a SDRAM for example),
RWDS must be tied to one during one of the RWDS signals, during the command/address
phase.
An additional t
CS#
t
CK
RWDS
DQ[7:0]
CS#
CK
RWDS
DQ[7:0]
Fixed latency mode
Some devices or some applications may not want to operate with a variable latency time as
described above.
The latency can be forced to 2 x t
OCTOSPI_HLCR.
In this Fixed latency mode, the state of the RWDS signal is not taken into account by the
OCTOSPI and an additional latency is always added leading to a fixed 2 x t
568/2301
duration is added by the OCTOSPI to meet the device request.
ACC
Figure 78. HyperBus read operation with additional latency
=Read Write Recovery
RWR
High = 2x Latency Count
Low = 1x Latency Count
47:40 39:32 31:24 23:16 15:8
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Figure 79. HyperBus write operation with additional latency
t RWR = Read Write Recovery
High = 2x Latency Count
Low = 1x Latency Count
47:40 39:32 31:24 23:16 15:8
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Additional Latency
Latency Count 1
7:0
Additional Latency
Latency Count 1
7:0
by setting the Latency mode (LM) bit of
ACC
RM0432 Rev 6
t = Access
ACC
Latency Count 2
Memory drives DQ[7:0]
and RWDS
t ACC = Initial Access
CK and Data
Latency Count 2
are center aligned
Dn
A
Host drives DQ[7:0]
and RWDS
RM0432
RWDS and Data
are edge aligned
Dn Dn Dn+1 Dn+1
A B A B
MSv43495V1
Dn Dn+1 Dn+1
B A B
MSv43496V1
latency time.
ACC