ST STM32L4+ Series Reference Manual page 792

Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only
PSSI signal
name
PSSI_PDCK
PSSI_D[15:0]
PSSI_DE
PSSI_RDY
Table 166
Internal
signal
name
pssi_it
pssi_dma
pssi_hclk
25.3.3 PSSI clock
The AHB clock frequency must be at least 2.5 times higher than the PSSI_PDCK frequency.
At frequency ratios lower than 2.5, data might be corrupted or lost during transfers.
Data transfers are synchronous with PSSI_PDCK. The PSSI_PDCK polarity can be
configured as follows, through CKPOL bit (bit 5 of PSSI_CR):
•
When CKPOL=0
–
–
•
When CKPOL=1
–
–
25.3.4 PSSI data management
Data direction
The direction of data transfers is configured through the OUTEN control bit (bit 31 of
PSSI_CR):
•
When OUTEN is cleared to 0 (default setting), the PSSI operates in receive mode and
the data is input on the data pins.
•
When OUTEN is set to 1, the peripheral operates in transmit mode and the data is
output on the data pins.
OUTEN can be modified only when the ENABLE bit is cleared to 0.
792/2301
Table 165. PSSI input/output pins
DCMI signal it
is shared with
DCMI_PIXCK
DCMI_D[13:0]
DCMI_HSYNC
DCMI_VSYNC
shows the PSSI internal input/output signals.
Table 166. PSSI internal input/output signals
Signal type
Output Interrupt
Output DMA request
Input AHB clock
Input pins are sampled on PSSI_PDCK falling edge
Output pins are driven on PSSI_PDCK rising edge
Input pins are sampled on PSSI_PDCK rising edge
Output pins are driven on PSSI_PDCK falling edge
Signal type
Input Parallel Data clock input
Data output when transmitting, data input when
Input/output
receiving
Data enable signal: data valid signal when receiving
Input
or flow control signal when transmitting
Ready signal: flow control signal when receiving or
Output
data valid signal when transmitting
RM0432 Rev 6
Description
Description