ST STM32L4+ Series Reference Manual page 955

RM0432
MRD_TIME = (t
•
t
HS->LP
•
t
LP->HS
•
t
LPDT
mode exit (according to the D-PHY specification, this value is always 11 bits in LP, or
22 TX escape clock cycles);
• t
lprd
•
t
read
• t
BTA
It is recommended to keep the maximum number of bytes read from the peripheral to a
minimum to have sufficient time available to issue the read commands in a line time. Ensure
that MRD_TIME x Lane byte clock period is less than LPSIZE x 16 x escape clock period of
the host, otherwise, the read commands are dispatched on the last line of a frame. If it is
necessary to read a large number of parameters (> 16), increase the MRD_TIME while the
read command is being executed. When the read has completed, decrease the MRD_TIME
to a lower value.
If a read command is issued on the last line of a frame, the LTDC interface is halted and
stays halted until the read command is in progress. The video transmission should be
stopped during this period.
30.9.5 Clock lane in Low-power mode
To reduce the power consumption of the D-PHY, the DSI Host, when not transmitting in the
High-Speed mode, allows the clock lane to enter into the Low-power mode. The controller
automatically handles the transition of the clock lane from HS (Clock lane active sending
clock) to LP state without direct intervention by the software. This feature can be enabled by
configuring the DPCC and the ACR bits of the DSI_CLCR register.
In the Command mode, the DSI Host can place the clock lane in the Low-Power mode when
it does not have any HS packets to transmit.
In the Video mode (LTDC interface), the DSI Host controller uses its internal video and PHY
timing configurations to determine if there is time available for the clock line to enter the
Low-Power mode and not compromise the video data transmission of pixel data and sync
events.
Along with a correct configuration of the Video mode (see
description: Video mode on LTDC
by the clock lane to go from High-Speed to Low-Power mode and viceversa. The values
required can be obtained from the D-PHY specification: program the DSI_CLTCR register
with the following values:
•
HS2LP_TIME = Time from HS to LP in clock lane / Byte clock period in HS
(lanebyteclk)
•
LP2HS_TIME = Time from LP to HS in clock lane / Byte clock period in HS
(lanebyteclk)
Based on the programmed values, the DSI Host calculates if there is enough time for the
clock lane to enter the Low-Power mode during inactive regions of the video frame.
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
+ t
HS->LP LP->HS
= Time to enter the Low-Power mode;
= Time to leave the Low-Power mode;
= D-PHY timing related to Escape mode entry, LPDT command, and Escape
= Read command time in Low-Power mode (64 * TX esc clock);
= Time to return the read data packet from the peripheral;
= time to perform a bus turnaround (D-PHY dependent).
+ t + t + t + 2 x t
LPDT lprd read
interface), the DSI Host needs to know the time required
RM0432 Rev 6
) / lanebyteclkperiod, where:
BTA
Section 30.5: Functional
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