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RM0432
30.15.5
DSI Host LTDC Color Coding Register (DSI_LCOLCR)
Address offset: 0x0010
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31: 9 Reserved, must be kept at reset value
Bit 8 LPE: Loosely Packet Enable
Bits 7: 4 Reserved, must be kept at reset value
Bit 3: 0 COLC: Color Coding
30.15.6
DSI Host LTDC Polarity Configuration Register (DSI_LPCR)
Address offset: 0x0014
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31: 3 Reserved, must be kept at reset value
Bit 2 HSP: HSYNC Polarity
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit enables the loosely packed variant to 18-bit configuration
0: Loosely Packet variant disabled
1: Loosely Packet variant enabled
This field configures the DPI color coding
0000: 16-bit configuration 1
0001: 16-bit configuration 2
0010: 16-bit configuration 3
0011: 18-bit configuration 1
0100: 18-bit configuration 2
0101: 24-bit
0110-1111: Reserved
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
This bit configures the polarity of HSYNC pin.
0: HSYNC pin active high (default).
1: VSYNC pin active low.
24
23
22
Res.
Res.
Res.
8
7
6
LPE
Res.
Res.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
COLC[3:0]
20
19
18
Res.
Res.
Res.
4
3
2
Res.
Res.
HSP
rw
17
16
Res.
Res.
1
0
rw
17
16
Res.
Res.
1
0
VSP
DEP
rw
rw
987/2301
1044
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