ST STM32L4+ Series Reference Manual page 208

Power control (PWR)
Refer to
If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB
access is finished.
In Stop 0 mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started, it cannot be stopped except by a Reset. See
Section 44.3: IWDG functional
• real-time clock (RTC): this is configured by the RTCEN bit in the
control register (RCC_BDCR)
•
Internal RC oscillator (LSI): this is configured by the LSION bit in the
register
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the
domain control register
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1,
LPTIM2, I2Cx (x=1,2,3,4) U(S)ARTx(x=1,2...5), LPUART.
The DACx (x=1,2), the OPAMPs and the comparators can be used in Stop 0 mode, the
PVMx (x=1,2,3,4) and the PVD as well. If they are not needed, they must be disabled by
software to save their power consumptions.
The ADCx (x=1,2,3), temperature sensor and VREFBUF buffer can consume power during
the Stop 0 mode, unless they are disabled before entering this mode.
Exiting the Stop 0 mode
The Stop 0 mode is exit according
Refer to
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The
MSI selection allows wakeup at higher frequency, up to 48 MHz.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop 0 mode with HSI16. By keeping the internal regulator
ON during Stop 0 mode, the consumption is higher although the startup time is reduced.
When exiting the Stop 0 mode, the MCU is either in Run mode (Range 1 or Range 2
depending on VOS bit in PWR_CR1) or in Low-power run mode if the bit LPR is set in the
PWR_CR1 register.
208/2301
Table 31: Stop 0 mode
(RCC_CSR).
(RCC_BDCR).
Table 31: Stop 0 mode
for details on how to enter the Stop 0 mode.
description.
Section : Entering low-power
for details on how to exit Stop 0 mode.
RM0432 Rev 6
Backup domain
Control/status
mode.
Clock configuration register
RM0432
Backup