ST STM32L4+ Series Reference Manual page 582

Octo-SPI interface (OCTOSPI)
Interrupt event
Timeout
Status match
FIFO threshold
Transfer complete
Transfer error
19.6 OCTOSPI registers
19.6.1 OCTOSPI control register (OCTOSPI_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
31 30 29 28
Res. Res. FMODE[1:0]
rw rw
15 14 13 12
Res. Res. Res.
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:28 FMODE[1:0]: Functional mode
This field defines the OCTOSPI functional mode of operation.
00: Indirect-write mode
01: Indirect-read mode
10: Automatic-polling mode
11: Memory-mapped mode
If DMAEN = 1 already, then the DMA controller for the corresponding channel must be
disabled before changing the FMODE[1:0] value.
This field can be written only when BUSY = 0. In such case, the request from OCTOSPI to
DMA becomes inactive.
Bits 27:24 Reserved, must be kept at reset value.
Bit 23 PMM: Polling match mode
This bit indicates which method must be used to determine a match during the Automatic-
polling mode.
0: AND-match mode, SMF is set if all the unmasked bits received from the device match the
corresponding bits in the match register.
1: OR-match mode, SMF is set if any of the unmasked bits received from the device matches
its corresponding bit in the match register.
This bit can be modified only when BUSY = 0.
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Table 121. OCTOSPI interrupt requests
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
FTHRES[4:0]
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RM0432 Rev 6
Event flag
TOF
SMF
FTF
TCF
TEF
23 22 21 20
PMM APMS Res. TOIE
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7 6 5
FSEL DQM Res. Res.
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Enable control bit
TOIE
SMIE
FTIE
TCIE
TEIE
19 18 17
SMIE FTIE TCIE
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4 3 2 1
TCEN DMAEN ABORT
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RM0432
16
TEIE
rw
0
EN
rw