ST STM32L4+ Series Reference Manual page 901

RM0432
29.6 LTDC interrupts
The LTDC provides four maskable interrupts logically ORed to two interrupt vectors.
The interrupt sources can be enabled or disabled separately through the LTDC_IER
register. Setting the appropriate mask bit to 1 enables the corresponding interrupt.
The two interrupts are generated on the following events:
•
Line interrupt: generated when a programmed line is reached. The line interrupt
position is programmed in the LTDC_LIPCR register
•
Register reload interrupt: generated when the shadow registers reload is performed
during the vertical blanking period
•
FIFO underrun interrupt: generated when a pixel is requested from an empty layer
FIFO
•
Transfer error interrupt: generated when an AHB bus error occurs during data transfer
Those interrupts events are connected to the NVIC controller as described in the figure
below.
Interrupt event
Line
Register reload
FIFO underrun
Transfer error
Figure 203. Interrupt events
Line
Register reload
FIFO underrun
Transfer error
Table 196. LTDC interrupt requests
RM0432 Rev 6
LCD-TFT display controller (LTDC)
LTDC global interrupt
LTDC global error interrupt
Event flag
LIF
RRIF
FUDERRIF
TERRIF
MS19678V1
Enable control bit
LIE
RRIEN
FUDERRIE
TERRIE
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