ST STM32L4+ Series Reference Manual page 217

RM0432
5.4 PWR registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
5.4.1 Power control register 1 (PWR_CR1)
Address offset: 0x00
Reset value: 0x0000 0200 (This register is reset after wakeup from Standby mode)
31 30 29
Res. Res. Res. Res.
15 14 13
Res. LPR Res. Res.
rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 LPR: Low-power run
Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS: Voltage scaling range selection
Bit 8 DBP: Disable backup domain write protection
Note: Depending on the APB1 prescaler, there is a delay between writing to DBP and the
Bits 7:5 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. VOS[1:0]
rw rw
When this bit is set, the regulator is switched from main mode (MR) to low-power mode
(LPR).
00: Cannot be written (forbidden by hardware)
01: Range 1
10: Range 2
11: Cannot be written (forbidden by hardware)
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
effective disable/enable of the backup domain protection. Therefore, a dummy read
operation to PWR_CR1 register is needed just after writing to the DBP bit.
24 23 22
Res. Res. Res.
8 7 6
DBP Res. Res.
rw
RM0432 Rev 6
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. RRSTP Res.
rw rw
17 16
Res. Res.
1 0
LPMS[2:0]
rw rw
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