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Digital camera interface (DCMI)
Bit 0 CAPTURE: Capture enable
Note: The DMA controller and all DCMI configuration registers must be programmed correctly
24.5.2
DCMI status register (DCMI_SR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 FNE: FIFO not empty
Bit 1 VSYNC: Vertical synchronization
Bit 0 HSYNC: Horizontal synchronization
780/2301
0: Capture disabled
1: Capture enabled
The camera interface waits for the first start of frame, then a DMA request is generated to
transfer the received data into the destination memory.
In snapshot mode, the CAPTURE bit is automatically cleared at the end of the first frame
received.
In continuous grab mode, if the software clears this bit while a capture is ongoing, the bit is
effectively cleared after the frame end.
before enabling this bit.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit gives the status of the FIFO.
1: FIFO contains valid data.
0: FIFO empty
This bit gives the state of the DCMI_VSYNC pin with the correct programmed polarity. When
embedded synchronization codes are used, the meaning of this bit is the following:
0: active frame
1: synchronization between frames
In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in
DCMI_CR is set.
This bit gives the state of the DCMI_HSYNC pin with the correct programmed polarity. When
embedded synchronization codes are used, the meaning of this bit is the following:
0: active line
1: synchronization between lines
In case of embedded synchronization, this bit is meaningful only if the CAPTURE bit in
DCMI_CR is set.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
FNE
r
RM0432
17
16
Res.
Res.
1
0
VSYNC HSYNC
r
r
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