ST STM32L4+ Series Reference Manual page 683

RM0432
Figure 153. DMA requests in regular simultaneous mode when MDMA=0b10
ADC Master regular
ADC Slave EOC
ADC Slave regular
ADC Slave EOC
DMA request from
ADC Master
DMA request from
ADC Slave
ADC Master regular
ADC Master EOC
ADC Slave regular
ADC Slave EOC
DMA request from
ADC Master
DMA request from
ADC Slave
Trigger
CH1
CH2
Configuration where each sequence contains only one conversion
Figure 154. DMA requests in interleaved mode when MDMA=0b10
Trigger Trigger
CH1
Delay
CH2
Configuration where each sequence contains only one conversion
Trigger
CH1
CH2
Trigger
CH1 CH1
Delay Delay
CH2 CH2
RM0432 Rev 6
Analog-to-digital converters (ADC)
Trigger Trigger
CH1 CH1
CH2 CH2
Trigger
Trigger
CH1
Delay
Delay
CH2
MSv31033V2
CH1
CH2
MSv31034V2
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