ST STM32L4+ Series Reference Manual page 420

Chrom-ART Accelerator controller (DMA2D)
The color format are coded as follows:
•
Alpha value field: transparency
0xFF value corresponds to an opaque pixel and 0x00 to a transparent one.
•
R field for Red
•
G field for Green
•
B field for Blue
•
L field: luminance
This field is the index to a CLUT to retrieve the three/four RGB/ARGB components.
If the original format was direct color mode (ARGB/RGB), then the extension to 8-bit per
channel is performed by copying the MSBs into the LSBs. This ensures a perfect linearity of
the conversion.
If the original format is indirect color mode (L/AL), a CLUT is required and each pixel format
converter is associated with a 256 entry 32-bit CLUT.
If the original format does not include an alpha channel, the alpha value is automatically set
to 0xFF (opaque).
For the specific alpha mode A4 and A8, no color information is stored nor indexed. The color
to be used for the image generation is fixed and is defined in the DMA2D_FGCOLR for
foreground pixels and in the DMA2D_BGCOLR register for background pixels.
The order of the fields in the system memory is defined in
Color Mode
ARGB8888
RGB888
RGB565
ARGB1555
ARGB4444
L8
AL44
AL88
L4
A8
A4
The 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
Once the 32-bit value is generated, the alpha channel can be modified according to the
AM[1:0] field of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers as shown in
Table 65: Alpha mode
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Table 64. Data order in memory
@ + 3
A [7:0]
0
B [7:0]
1
G [7:0]
2
R [7:0]
3
R [4:0]G [5:3]
1 1
A [0]R [4:0]G [4:3]
1 1 1
A [3:0]R [3:0]
1 1
L [7:0]
3
A [3:0]L [3:0]
3 3
A [7:0]
1
L [3:0]L [3:0]
7 6
A [7:0]
3
A [3:0]A [3:0]
7 6
configuration.
RM0432 Rev 6
Table 64: Data order in
@ + 2
R [7:0]
0
R [7:0]
0
B [7:0]
2
G [7:0]
3
G [2:0]B [4:0] R
1 1 0
G [2:0]B [4:0] A [0]R
1 1 0
G [3:0]B [3:0] A
1 1 0
L [7:0]
2
A [3:0]L [3:0] A
2 2 1
L [7:0]
1
L [3:0]L [3:0] L
5 4 3
A [7:0]
2
A [3:0]A [3:0] A
5 4 3
@ + 1 @ + 0
G [7:0] B
0
G [7:0] B
0
R [7:0] G
1
B [7:0] R
3
[4:0]G [5:3] G [2:0]B
0 0
[4:0]G [4:3] G [2:0]B
0 0 0
[3:0]R [3:0] G [3:0]B
0 0
L [7:0] L
1
[3:0]L [3:0] A [3:0]L
1 0
A [7:0] L
0
[3:0]L [3:0] L [3:0]L
2 1
A [7:0] A
1
[3:0]A [3:0] A [3:0]A
2 1
RM0432
memory.
[7:0]
0
[7:0]
0
[7:0]
1
[7:0]
2
[4:0]
0
[4:0]
0
[3:0]
0
[7:0]
0
[3:0]
0
[7:0]
0
[3:0]
0
[7:0]
0
[3:0]
0