ST STM32L4+ Series Reference Manual page 704

Analog-to-digital converters (ADC)
Bit 31 SMPPLUS: Addition of one clock cycle to the sampling time.
To make sure no conversion is ongoing, the software is allowed to write this bit only when
ADSTART= 0 and JADSTART= 0.
Bit 30 Reserved, must be kept at reset value.
Bits 29:0 SMP[9:0][2:0]: Channel x sampling time selection
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
21.6.7 ADC sample time register 2 (ADC_SMPR2)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SMP15[0] SMP14[2:0]
rw rw rw
704/2301
1: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1
and ADC_SMPR2 registers.
0: The sampling time remains set to 2.5 ADC clock cycles remains
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
000: 2.5 ADC clock cycles
001: 6.5 ADC clock cycles
010: 12.5 ADC clock cycles
011: 24.5 ADC clock cycles
100: 47.5 ADC clock cycles
101: 92.5 ADC clock cycles
110: 247.5 ADC clock cycles
111: 640.5 ADC clock cycles
(which ensures that no conversion is ongoing).
Some channels are not connected physically. Keep the corresponding SMPx[2:0]
setting to the reset value.
28 27 26 25
Res. Res. SMP18[2:0]
rw rw
12 11 10 9
SMP13[2:0]
rw rw rw rw
24 23 22
SMP17[2:0]
rw rw rw
8 7 6
SMP12[2:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
SMP16[2:0]
rw rw rw rw
5 4 3 2
SMP11[2:0]
rw rw rw rw
RM0432
17 16
SMP15[2:1]
rw rw
1 0
SMP10[2:0]
rw rw